Programmable logic devices (PLD), which include application-specific integrated circuits and field-programmable gate arrays, are integrated circuits having programmable logic cores formed by uncommitted logic modules and routing interconnects that are able to implement a costumed logic design up to the logic capacity of the particular PLD. A PLD may include multiple random access memories (RAMs) that generally come in three different flavors, namely, dynamic random access memory (DRAM), static random access memory (SRAM), and register files. Typically, DRAMs are employed when a larger amount of memory is needed, and register files are employed when only a small amount of memory is required. SRAMs are utilized when the required amount of memory falls somewhere in the middle of the above-mentioned two situations.
Both DRAMs and SRAMs tend to have very small physical size per bit, but require a larger amount of operational overhead that includes hardware components such as refresh circuits, sense amplifier circuits, etc. and software for performing memory tests. On the other hand, register files are usually D-register flip-flops located in a compact, pre-routed block. Thus, register files have a much smaller operational overhead than those of DRAMs and SRAMs, but the size per bit for register files is much greater than those of DRAMs and SRAMs.
The present disclosure relates to the provision of a new type of memory that fills the gap between register files and SRAMs when the memory requirement is too big for register files, but too small for SRAMs from a size and power perspective.